(China (Mainland))
Product Summary
The XCR3256XL-TQG144CMN is a 256 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of 16 function blocks provide 6,000 usable gates. Pin-to-pin propagation delays are 7.5 ns with a maximum system frequency of 140 MHz.
Parametrics
XCR3256XL-TQG144CMN absolute maximum ratings: (1)Output High voltage IOH = -8 mA, VOH: 2.4V; (2)Output Low voltage for 3.3V outputs IOL = 8 mA, VOL: 0.4 V; (3)Input leakage current VIN = GND or VCC, IIL: -10 to 10 μA; (4)I/O High-Z leakage current VIN = GND or VCC, IIH: -10 to 10 μA; (5)Standby current VCC = 3.6V, ICCSB: 100 μA; (6)Dynamic current(3,4) f = 1 MHz, ICC: 2 mA; f = 50 MHz, ICC: 60 mA; (7)Input pin capacitance(5) f = 1 MHz, CIN: 8 pF; (8)Clock input capacitance(5) f = 1 MHz, CCLK: 5 to 12 pF; (9)I/O pin capacitance(5) f = 1 MHz, CI/O: 10 pF.
Features
XCR3256XL-TQG144CMN features: (1)Lowest power 256 macrocell CPLD; (2)7.5 ns pin-to-pin logic delays; (3)System frequencies up to 140 MHz; (4)256 macrocells with 6,000 usable gates; (5)Available in small footprint packages; (6)Optimized for 3.3V systems; (7)Advanced system features, In-system programming; Input registers; Predictable timing model; Up to 23 clocks available per function block; Excellent pin retention during design changes; Full IEEE Standard 1149.1 boundary-scan (JTAG); Four global clocks; Eight product term control terms per function block; (8)Fast ISP programming times; (9)Port Enable pin for additional I/O; (10)2.7V to 3.6V supply voltage at industrial grade voltage range; (11)Programmable slew rate control per output; (12)Security bit prevents unauthorized access; (13)Refer to XPLA3 family data sheet (DS012) for architecture description.
Diagrams
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